Is SMIC N+3's Metal Pitch Smaller than Intel 18A's?

SMIC has achieved TSMC N6-class logic density with its third-generation 7nm (N+3) process used in Huawei’s Kirin 9030 chip, according to SemiAnalysis. While lacking EUV lithography, SMIC uses aggressive DUV multi-patterning and design-technology co-optimization (DTCO) to reach a transistor density of 113.4 MTr/mm².

How does SMIC reach 7nm density without EUV?

SMIC uses a combination of self-aligned quadruple patterning (SAQP) and aggressive design-technology co-optimization (DTCO) to bypass the need for Extreme Ultraviolet (EUV) lithography. According to SemiAnalysis, the N+3 process achieves a minimum metal pitch (M0) of 32.5 nm, which is tighter than the 36 nm pitch found in Intel’s Panther Lake CPUs on 18A.

This density comes at a cost. SemiAnalysis reports that N+3 requires far more aggressive DUV multi-patterning than TSMC’s N6. This increases mask counts, overlay sensitivity, and overall process complexity. While SMIC’s Bohr density of 113.4 MTr/mm² slightly exceeds TSMC N6’s 107.7 MTr/mm², the process is less mature and more expensive to produce.

Did you know? SAQP allows a fab to create four times the number of lines a single lithography pass can resolve. It’s a complex “spacer” process that lets SMIC hit tighter pitches without the multi-million dollar EUV machines blocked by US export controls.

Why is the Kirin 9030 slower than Apple and Qualcomm chips?

Transistor density doesn’t automatically equal performance. SemiAnalysis finds that the Kirin 9030 Pro performs similarly to three-year-old Android flagships and trails significantly behind current offerings from Apple, Qualcomm, and MediaTek. The gap is most evident in power efficiency.

The Kirin 9030’s prime core is roughly equivalent to a 2021-era Arm Cortex-X2 design. In contrast, SemiAnalysis notes that Apple’s efficiency cores can deliver 20% higher integer performance while drawing only 1 W, compared to 4.5 W for Huawei’s prime core. This occurs because leading-edge nodes like TSMC N3P provide a superior voltage-frequency curve, allowing competitors to use more transistors for wider cores and larger caches without overheating.

Huawei has attempted to recover some ground through microarchitecture. According to the report, the Kirin 9030’s middle and tiny cores saw per-clock integer performance gains of 17% and 14%, respectively, over the previous Kirin 9020.

What is Huawei’s “LogicFolding” strategy?

Because planar scaling with DUV is hitting a wall, Huawei is pivoting toward a system-technology co-optimization (STCO) approach called “LogicFolding.” According to SemiAnalysis, this is an aggressive 3D stacking method where active logic is split across multiple dies bonded face-to-face at an ultra-fine pitch.

The goal is to shorten signal paths and reduce the energy spent driving long interconnects. Huawei’s roadmap targets a prime core frequency of roughly 5 GHz by 2031, a jump from the 2.75 GHz seen in the Kirin 9030. SemiAnalysis reports that Huawei claims this approach will allow them to reach “foundry 14A-equivalent density” by 2031 by measuring density per package footprint rather than per die.

Pro Tip: When reading chip density claims, distinguish between “planar density” (transistors on a single layer) and “package density” (transistors stacked in 3D). 3D stacking can make a chip look more advanced than the underlying fabrication process actually is.

How are export controls reshaping the Chinese chip ecosystem?

US restrictions on EUV and advanced Electronic Design Automation (EDA) tools haven’t stopped production, but they’ve forced a domestic pivot. SemiAnalysis notes that Huawei, SMIC, and Chinese academic institutions are building their own EDA tools and flows to support unique architectures like LogicFolding.

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This knowledge is also spreading. SMIC is reportedly licensing its N+2 and N+3 processes to other fabs like HLMC/Hua Hong under government direction. SemiAnalysis suggests this creates a broader ecosystem where AI chip designers, such as Alibaba’s T-Head or Cambricon, can benefit from the same process learning, making sanctions on a single company like SMIC less effective over time.

Comparison: SMIC N+3 vs. TSMC N6

Metric	SMIC N+3	TSMC N6
Bohr Density	113.4 MTr/mm²	107.7 MTr/mm²
M0 Metal Pitch	32.5 nm	~40 nm
Lithography	DUV (SAQP)	EUV / DUV
Process Maturity	Low (High Complexity)	High (Mature)

Frequently Asked Questions

Can SMIC catch up to TSMC without EUV?
According to SemiAnalysis, SMIC can match the density of older nodes like N6 using DUV and DTCO, but it cannot match the efficiency, cost, or performance of leading-edge EUV nodes like N3P.

What is the Kirin 9030’s main advantage?
The Kirin 9030 shows that Huawei can maintain a functional, high-end SoC pipeline despite severe trade restrictions, utilizing domestic fabrication and design tools.

What happens if LogicFolding works?
If successful, Huawei could recover the frequency and performance gaps it currently faces by stacking logic vertically to shorten the distance data must travel, bypassing some of the limits of planar scaling.

What do you think about China’s pivot to 3D stacking? Will LogicFolding be enough to close the gap with Apple and Qualcomm? Let us know in the comments or subscribe to our newsletter for more deep dives into semiconductor engineering.

Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?